1. Field of the Invention
The present disclosure relates generally to flash memory devices and, more particularly, to a flash memory device with a program data cache and a method for programming the same.
A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 2006-84270 filed on Sep. 1, 2006, the entire contents of which are hereby incorporated by reference.
2. Discussion of Related Art
There has been a surge in demand for both volatile and nonvolatile memories for use as memory storage components in a number of electronic devices. These electronic devices include a number of mobile devices such as, for example, MP3 players, personal multimedia players (PMP), mobile phones, notebook computers, personal digital assistants (PDA), and so on. Mobile devices typically require storage units with a large storage capacity but that are also small in size. One way to produce storage devices with a large storage capacity but small size is to manufacture a multi-bit memory device where each memory cell stores 2 bits or more of data.
Conventionally, in most memory devices, only 1-bit data is stored in a single memory cell. Specifically, in storing 1-bit data in a single memory cell, the memory cell is conditioned in a threshold voltage, corresponding to one of two threshold voltage states. Namely, the memory cell has one of two states that represent data ‘1’ and data ‘0’. On the other hand, when a single memory cell stores 2-bit data, the memory cell is conditioned in a threshold voltage that corresponds to one of four threshold voltage states. In other words, the memory cell has one of four states representing data ‘11’, data ‘10’, data ‘00’, and data ‘01’.
Because of an increase in the number of threshold voltage states, it may be beneficial to ensure that each voltage distribution is confined to a corresponding window such that there is no overlap between the voltage distributions. Furthermore, there should be sufficient margin between the voltage distributions to ensure that there are no programming errors.
In order to ensure that threshold voltage distribution profiles are confined within the corresponding windows associated with the four data states, it may be beneficial to adjust the threshold voltages within each window. One method of adjusting the threshold voltage within a corresponding window involves the use of a programming method using an ISPP (incremental step pulse programming) scheme. In the ISPP scheme, a threshold voltage increases in steps with an increase in the number of programming operations. Furthermore, it may be possible to control the distribution of threshold voltages by establishing the incremental rate of the program voltage to be small. This means that there is a sufficient margin between the threshold voltages of the various data states. However, a smaller incremental rate of program voltage lengthens a time required for programming a memory cell into a desired state. Therefore, the incremental rate of program voltage is established in consideration of programming time. Thus, for at least this reason, even with the ISPP scheme, distribution profiles of threshold voltages corresponding to the data states are typically wider than the desired width.
FIG. 1 is a schematic diagram showing a sequence in a programming scheme used for programming a general flash memory device. Referring to FIG. 1, a programming operation of the flash memory device is carried out in units of two adjacent word lines. Specifically, a page buffer 10 is electrically connected to bit lines corresponding to even and odd column addresses. In the programming operation, memory cells are programmed in the sequence of MC1->MC2->MC3->MC4 by the page buffer 10. In addition, a program voltage is applied to word lines WL_N-1 and WL_N.
In this case, a threshold voltage of the first programmed memory cell MC1 may be affected by programming carried out on its adjacent memory cells MC2, MC4, and MC4. In particular, a threshold voltage distribution profile of the memory cell MC1 may become wider because of coupling effects between the adjacent memory cells during the programming operation. Moreover, this phenomenon occurs at all the memory cells MC1˜MC4 programmed by the page buffer 10. Such a coupling effect is referred to as ‘F-poly coupling’. In a conventional programming method, the F-poly coupling effects are generated between all of adjacent memory cells being programmed.
FIG. 2 is a diagram illustrating program states of the memory cell MC1 affected from the aforementioned coupling effects between memory cells. Referring to FIG. 2, the memory cell MC1 is programmed into one of four data states ‘11’, ‘01’, ‘10’, and ‘00’. A programming operation for writing 2-bit data in the memory cell MC1 may be carried out by various means. For example, the programming operation may begin after loading all LSB and MSB data bits into the page buffers 10 and 20. On the other hand, the programming operation may be carried out with first programming a LSB data bit and next programming an MSB data bit.
A memory cell is programmed into one of the data states ‘11’, ‘01’, ‘10’, and ‘00’. Of the disclosed data states, the state ‘11’ corresponds to an erased memory cell. Furthermore, a memory cell with the state ‘01’ is at a higher threshold voltage level than a memory cell with the state ‘11’. In addition, a memory cell with the state ‘10’ is at a higher threshold voltage level than a memory cell with the state ‘01’ and a memory cell with the state ‘00’ is at a higher threshold voltage level than a memory cell with the state ‘10’.
As illustrated in FIG. 2, after the programming operation carried out by the aforementioned method, the memory cell MC1 should preferably have a narrow distribution profile such as a state 31, 32, or 33. However, charges accumulate in a floating gate of the memory cell MC1 because of the F-poly coupling effect. This accumulation of charges in the memory cell MC1 because of the F-poly coupling effect may extend the voltage distribution profile of the memory cell MC1 to undesired states such as 34, 35, or 36, as shown in FIG. 2.
The extension of the threshold voltage distribution profile by the programming operations for adjacent memory cells may degrade the reliability of reading operations for the memory cell. This problem may be exacerbated as the number of data bits stored in a single memory cell increase. There is therefore a need for a programming method that programs a multi-bit memory cell without extending the voltage distribution profile of the memory cell beyond a desirable threshold.
The present disclosure is directed towards overcoming one or more limitations associated with the conventional programming of memory cells.